This invention relates generally to cooling assembly components, and more particularly to a folded-sheet-metal heatsink for cooling closely packaged heat-producing devices.
Contemporary memory systems employed in high-performance computing machinery are generally composed of one or more dynamic random-access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer-system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges relating to overall system reliability, because customers expect new computer systems to have markedly improved mean-time-between-failure (MTBF), and to offer additional functions, increased performance, increased storage, lower operating costs, simplified upgrade, and reduced environmental impact (such as space, power and cooling).
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 108, buffer devices 112, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 210 which includes a synchronous memory module 220 that is directly (i.e. point-to-point) connected to a memory controller 214 via a bus 240, and which further includes logic circuitry 224 (such as an application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller 214. The memory module 220 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (I2C) control bus 234, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. No. 5,513,135, U.S. Pat. No. 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of functions is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 310 that includes up to four registered DIMMs 340 on a traditional multi-drop stub bus. The subsystem includes a memory controller 320, an external clock buffer 330, registered DIMMs 340, an address bus 350, a control bus 360 and a data bus 370 with terminators 395 on the address bus 350 and the data bus 370. Although only a single memory channel is shown in FIG. 3, systems produced with these modules often included more than one discrete memory channel from the memory controller, with each of the memory channels operated singly (when a single channel was populated with modules) or in parallel (when two or more channels where populated with modules) to achieve the desired system functionality and/or performance.
FIG. 4, from U.S. Pat. No. 6,587,912 to Bonella et al., depicts a synchronous memory module 410 and system structure in which the repeater hubs 420 include local re-drive of the address, command and data to the local memory devices 401 and 402 via buses 421 and 422; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 400.
As is evident from the prior-art references, the computer and memory industries have continuously strived to maximize overall system performance and memory subsystem value by utilizing technology improvements (e.g., increased circuit density and reduced circuit power), increased functionality in the memory subsystem (enabled by these same factors), and alternate bus structures. However, one result of the increased memory-subsystem performance and function, in conjunction with the integration and use of hub devices and many external DRAM devices, is an increase in the amount of heat generated on the DIMM. Indeed, memory DIMMs today are observed to have heatsinks extending largely over the whole of the surface of the DIMM. However, due to factors such as an incomplete understanding of the nature of the heat flow, heatsinks to date have not typically been optimized. Consequently, overheating of one or more of the devices can occur, causing excessive failure rates due to exaggerated leakage of the DRAM devices, and also causing slower transistor switching times that in turn cause data upsets. Moreover, leakage currents in hub chips (also referred to as hub devices, buffer chips or buffer devices) and DRAMs are observed to increase with temperature, so that these devices draw even more power, and incur even higher temperatures, as a result of inadequate cooling. Higher temperatures can also increase the rate of corrosion, metal fatigue, and other physical processes that can eventually result in a memory DIMM failure and potential loss of data.
Therefore, the need exists for an improved heatsink design that can lower both the hub-chip and the DRAM temperatures. This improved design should ideally allow reduced spacing between DIMMs, and should not dramatically increase the air-pressure drop through the heatsink. Such a solution, by providing lower DRAM and hub-chip temperatures, would reduce the DIMM failure rate, leakage power, and therefore system-level cooling requirements. For all these reasons, such a solution would reduce system cost. Additional benefits would include increased operating and test margins.